The MAX9209/MAX9213 serialize 21 bits of LVTTL/LVCMOS parallel input data to three LVDS outputs. A parallel rate clock on a fourth LVDS output provides
timing for deserialization.
The MAX9209/MAX9213 feature programmable DC balance,
which allows isolation between the serializer and
deserializer using AC-coupling. The DC balance circuits
on each channel code the data, limiting the imbalance
of transmitted ones and zeros to a defined range. The
companion MAX9210/MAX9214 deserializers decode
the data. When DC balance is not programmed, the
serializers are compatible with non-DC-balanced, 21-bit
serializers such as the DS90CR215 and DS90CR217.
Two frequency ranges and two DC-balance default
conditions are available for maximum replacement flexibility
and compatibility with existing non-DC-balanced
serializers.
The MAX9209/MAX9213 are available in TSSOP and
space-saving thin QFN packages.
Key Features
Applications/Uses
Programmable DC-Balanced or Non-DC-Balanced Operation
DC Balance Allows AC-Coupling for Ground-Shift Tolerance
As Low as 8MHz Operation
Pin Compatible with DS90CR215 and DS90CR217 in Non-DC-Balanced Mode
Integrated 110Ω (DC-Balanced) and 410Ω (Non-DC-Balanced) Output Resistors
5V Tolerant LVTTL/LVCMOS Data Inputs
PLL Requires No External Components
Up to 1.785Gbps Throughput
LVDS Outputs Meet IEC 61000-4-2 and ISO 10605 Requirements
LVDS Outputs Conform to ANSI TIA/EIA-644 LVDS Standard
Low-Profile 48-Lead TSSOP and Space-Saving QFN Packages
Notes: **This pricing is BUDGETARY, for comparing similar parts. Prices are in
U.S. dollars and subject to change. Quantity pricing may vary
substantially and international prices may differ due to local
duties, taxes, fees, and exchange rates. For volume-specific prices
and delivery, please see the price and availability page
or contact an authorized distributor.
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