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MAX1208
12-Bit, 80Msps, 3.3V ADC


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Description
FULL DATA SHEET (PDF, 1MB)
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The MAX1208 is a 3.3V, 12-bit, 80Msps analog-to-digital converter (ADC) featuring a fully differential wideband track-and-hold (T/H) input amplifier, driving a low-noise internal quantizer. The analog input stage accepts single-ended or differential signals. The MAX1208 is optimized for low power, small size, and high dynamic performance in baseband applications.

Powered from a single 3.0V to 3.6V supply, the MAX1208 consumes only 373mW while delivering a typical signal-to-noise (SNR) performance of 68.2dB at an input frequency of 32.5MHz. In addition to low operating power, the MAX1208 features a 3µW power-down mode to conserve power during idle periods.

A flexible reference structure allows the MAX1208 to use the internal 2.048V bandgap reference or accept an externally applied reference. The reference structure allows the full-scale analog input range to be adjusted from ±0.35V to ±1.15V. The MAX1208 provides a common-mode reference to simplify design and reduce external component count in differential analog input circuits.

The MAX1208 supports both a single-ended and differential input clock drive. Wide variations in the clock duty cycle are compensated with the ADC's internal duty-cycle equalizer (DCE).

ADC conversion results are available through a 12-bit, parallel, CMOS-compatible output bus. The digital output format is pin selectable to be either two's complement or Gray code. A data-valid indicator eliminates external components that are normally required for reliable digital interfacing. A separate digital power input accepts a wide 1.7V to 3.6V supply, allowing the MAX1208 to interface with various logic levels.

The MAX1208 is available in a 6mm x 6mm x 0.8mm, 40-pin thin QFN package with exposed paddle (EP), and is specified for the extended industrial (-40°C to +85°C) temperature range.

See a parametric table of the complete family of pin-compatible, 12-/14-bit high-speed ADCs.

Key Features   Applications/Uses
  • Excellent Dynamic Performance
    • 68.2dB/68.0dB SNR at fIN = 3MHz/70MHz
    • 89.3dBc/85.1dBc SFDR at fIN = 3MHz/70MHz
  • 3.3V Low-Power Operation
    • 373mW (Single-Ended Clock Mode)
    • 399mW (Differential Clock Mode)
    • 3µW (Power-Down Mode)
  • Differential or Single-Ended Clock
  • Fully Differential or Single-Ended Analog Input
  • Adjustable Full-Scale Analog Input Range: ±0.35V to ±1.15V
  • Common-Mode Reference
  • CMOS-Compatible Outputs in Two's Complement or Gray Code
  • Data-Valid Indicator Simplifies Digital Design
  • Data Out-of-Range Indicator
  • Miniature, 40-Pin Thin QFN Package with Exposed Paddle
  • Evaluation Kit Available (Order MAX1211EVKIT)

 
  • Communication Receivers: Cellular, Point-to-Point Microwave, HFC, WLAN
  • Low-Power Data Acquisition
  • Portable Instrumentation
  • Ultrasound and Medical Imaging

    Key Specifications:   High-Speed ADCs (> 5Msps)
    Part Number Resolution (Bits) Sample Rate (max) (Msps) Sample Rate (max) (Msps) AC Specs @ fIN (MHz) SFDR (dBc) SINAD (dB) SNR (dB) THD (db) INL (±LSB) DNL (±LSB)
    MAX1208  12 80 80 32.5 88.2 68.1 68.2 -85 0.65 0.35
    See All High-Speed ADCs (> 5Msps) (81)

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    Document Ref.: 19-1002; Rev 0; 2004-08-12
    This page last modified: 2008-07-25



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