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The MAX19541 monolithic 12-bit, 125Msps analog-todigital
converter (ADC) is optimized for outstanding
dynamic performance at high-IF frequencies of
300MHz and beyond. This device operates with conversion
rates up to 125Msps while consuming only
861mW.
At 125Msps and an input frequency of 240MHz, the
MAX19541 achieves a spurious-free dynamic range
(SFDR) of 71.5dBc. The MAX19541 features an excellent
signal-to-noise ratio (SNR) of 65.4dB at 10MHz that
remains flat (within 3dB) for input tones up to 250MHz.
This makes the MAX19541 ideal for wideband applications
such as power-amplifier predistortion in cellular
base-station transceiver systems.
The MAX19541 operates in either parallel mode where
the data outputs appear on a single parallel port at the
sampling rate, or in demux parallel mode, where the outputs
appear on two separate parallel ports at one-half
the sampling rate. See the Mode of Operation section.
The MAX19541 operates on a single 1.8V supply. The
analog input is differential and can be AC- or DC-coupled.
The ADC also features a selectable on-chip
divide-by-2 clock circuit that allows clock frequencies
as high as 250MHz. This helps to reduce the phase
noise of the input clock source, allowing for higher
dynamic performance. For best performance, a differential
LVPECL sampling clock is recommended. The
digital outputs are CMOS compatible and the data format
can be selected to be either two's complement or
offset binary.
A pin-compatible, 12-bit, 170Msps version of the
MAX19541 is also available. Refer to the MAX19542
data sheet for more information.
The MAX19541 is available in a 68-pin QFN with
exposed paddle (EP) and is specified over the extended
(-40°C to +85°C) temperature range.
See a parametric table of the complete family of pin-compatible, 12-bit high-speed ADCs.
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