The DS3102 is a low-cost, feature-rich timing IC for telecom timing cards. With 8 input clocks, the device directly accepts both line timing from a large number of line cards and external timing from external DS1/E1 BITS transceivers. The DS3102 continually monitors all input clocks and performs automatic hitless reference switching if the primary reference fails. The T0 DPLL complies with the Stratum 3 requirements of GR-1244, GR-253, and the requirements of G.813 and G.8262. The highly programmable DS3102 support numerous input and output frequencies including rates required for SONET/SDH, Synchronous Ethernet (1G, 10G, and 100Mbps), wireless base stations, and CMTS systems. PLL bandwidths from 0.5mHz to 400Hz are supported, and a wide variety of PLL characteristics and device features can be configured to meet the needs of many different applications. Two DS3102 devices can be configured in a master/slave arrangement for timing card equipment protection.
The DS3102 register set is backward compatible with Semtech's ACS8522 timing card IC. The DS3102 has a different package and pin arrangement than the
ACS8522.
Key Features
Applications/Uses
Synchronization for Stratum 3/4E/4, SMC, and SEC
Meets Requirements of GR-1244 Stratum 3, GR-253, G.812 Type IV, G.813, and G.8262
Stratum 3 Holdover Accuracy with Suitable External Oscillator
Programmable Bandwidth: 0.5mHz to 400Hz
Hitless Reference Switching on Loss of Input
Automatic or Manual Phase Build-Out
Frequency Conversion Among SONET/SDH, PDH, Ethernet, Wireless, and CMTS Rates
8 Input Clocks
Four CMOS/TTL Inputs (≤ 125MHz)
Four LVDS/LVPECL/CMOS/TTL Inputs (≤ 156.25MHz)
Three Optional Frame-Sync Inputs (CMOS/TTL)
Continuous Input Clock Quality Monitoring
Numerous Input Clock Frequencies Supported:
SONET/SDH: 6.48, N x 19.44, N x 51.84MHz
Ethernet xMII: 2.5, 25, 125, 156.25MHz
PDH: N x DS1, N x E1, N x DS2, DS3, E3
Frame Sync: 2kHz, 4kHz, 8kHz
Custom: Any Multiple of 2kHz Up to 131.072MHz, Any Multiple of 8kHz Up to 155.52MHz
7 Output Clocks
Three CMOS/TTL Outputs (≤ 125MHz)
Two LVDS/LVPECL Outputs (≤ 312.50MHz)
Two Dual CMOS/TTL and LVDS/LVPECL Outputs
Five CMOS Outputs Have Additional Output Pins That Can Be Powered at 2.5V or 3.3V
Numerous Output Clock Frequencies Supported:
SONET/SDH: 6.48, N x 19.44, N x 51.84MHz
Ethernet xMII: 2.5, 25, 125, 156.25, 312.5MHz
PDH: N x DS1, N x E1, N x DS2, DS3, E3
Other: 10, 10.24, 13, 30.72MHz
Frame Sync: 2kHz, 8kHz
Custom Clock Rates: Any Multiple of 2kHz Up to 77.76MHz, Any Multiple of 8kHz Up to 311.04MHz, Any Multiple of 10kHz Up to 388.79MHz
General
Internal Compensation for Master Clock Oscillator
SPI™ Processor Interface
1.8V Operation with 3.3V I/O (5V Tolerant)
Industrial Temperature Range
SONET/SDH Equipment Clocks (SECs)
Synchronous Ethernet Equipment Clocks (EECs)
Timing Card IC in WAN Equipment Including MSPPs, Ethernet Switches, Routers, DSLAMs, and Wireless Base Stations
* Some packages have variations, listed on the drawing. "PkgCode/Variation" tells which variation the product uses. Note that "+", "#", "-" in the part number suffix describes RoHS status. Package drawings may show a different suffix character.
Devices:
1-2
of
2
DS3102
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Package:
TYPE PINS FOOTPRINT
DRAWING CODE/VAR *
Temp
RoHS/Lead-Free? Materials Analysis
DS3102GN+
CSBGA;81 pin;
Dwg: 21-0360 (PDF)
Use pkgcode/variation: X81+1*
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